Topological Insulators (TIs) are very interesting due to the notion that a local excitation (a surface state or an edge state) is created by a global property of the system (a band structure with nontrivial topology) [1]. These topological surface states hold great promise for scatter-free transport channels. Topological qubits have high potential for fault-tolerant quantum computing [2].

Topological crystalline insulators are a special subclass where the topological protection is caused by the mirror symmetries of the crystal. The breaking of the topological phase can thus be controlled by deforming the crystal structure allowing for more control. Measuring these topological states electronically has proven difficult due to the high bulk conductance in metallic T(C)I’s overshadowing the transport through the topological states. Therefore, we propose the semiconductor TCI SnTe as a material of interest to electronically measure the topological surface states.

Alloying the topological crystalline insulator SnTe with Pb reduces the formation of Sn vacancies while maintaining its topological phase [3, 4]. These vacancies are the cause of the high p-type carrier density of the system [4]. By varying the incorporation of Pb, the density of Sn vacancies can be reduced and hence electrostatic tunability of the nanowire can be facilitated. Nanowires with a high aspect ratio have a high surface-to-volume ratio allowing for more accessible measurements of the topological surface states.

We present the finely controlled growth of vapor-solid-grown single crystalline Pb1-xSnxTe arrays with high yield and verticality (Figure 1a). The Sn to Pb ratio and the aspect ratio can be tuned by varying the growth parameters. Furthermore, we present a phenomenological growth model to describe the morphology of Pb0.5Sn0.5Te nanowires for varying growth parameters (Figure 1b). These results will allow us to optimize the morphology of the nanowires for different device designs.