The integration of two-dimensional (2D) materials into solid-state electronic devices and circuits could pave the way to extend Moore’s law and advance beyond-CMOS (complementary metal–oxide–semiconductor) technology.1 The variety of 2D materials covers metallic (graphene), semiconductor (e.g., MoS2) and insulator (h-BN) systems with their own unique physical properties. In addition, layer-by-layer stacking of 2D materials enables the assembly of 2D hetero-structures, which could lead to innovative devices and new applications. However, full exploitation of most circuit applications depends on wafer-scale 2D layer synthesis, device fabrication, and integration.2

Here, the fabrication steps and basic characterization of metal-insulator-metal devices made from single layer graphene (SLG) and few layer hexagonal boron nitride (hBN) films are described. The material was grown by (metal organic) chemical vapour deposition (MOCVD) in an AIXTRON CCS reactor on c-plane sapphire wafers with a diameter of 50 mm. The as-deposited 2D layers were delaminated and wet transferred to the silicon target substrate. Processes such as lithography, ion beam etching, metal deposition and lift-off have been implemented to fabricate first devices. Insulating hBN between different metals is investigated for memristive devices, while hBN/SLG stacks are used for field effect transistors. The presentation will address device fabrication and electrical characterization.

This work was in part funded by the Federal Ministry of Education and Research (BMBF, Germany) in the projects NEUROTEC (Project No. 16ME0398K) and NeuroSys (Project No. 03ZU1106AB) and is based on the Juelich Aachen Research Alliance (JARA-FIT).