Fraunhofer-Institut für Keramische Technologien und Systeme IKTS
Semiconductor industry is continuing the downsizing of device structures and of on-chip interconnect dimensions, both for performance reasons but also from economic reasons, to minimize the required die size. This trend has implications for the layout of guard ring structures, i.e. metallic non-functional structures in the back end of line (BEoL) stack at the periphery of these microchips that are designed to protect the active die area from damages. These metallic structures have to be constructed to be efficient to stop microcracks and, on the other hand, the dimension of these structures has to be as small as possible. In this work, we introduce an in-situ experiment to study mechanical degradation and failure mechanisms in the BEoL stack, to ensure the mechanical robustness of microchips for future technology nodes. In addition, a suitable FEM simulation of the sample structure is developed by using the acquired process settings.
To investigate the effects of micromechanical loading on the BEoL stack, a novel micromechanical in-situ experiment was integrated into an X-ray microscope (ZEISS Xradia 800 Ultra). This experimental assembly enables high resolution imaging of the 3D-patterned sample structures and defects such as microcracks in 2D and 3D with a resolution of up to 50 nm during in-situ testing. Performing tomographies allows non-destructive 3D visualization of the inside throughout the entire experiment and thus 3D tracking of the crack path during the whole duration. A suitable sample geometry was found by FEM simulation of a homogeneous silicon specimen which was eventually realized by focused ion beam (FIB) milling on the prepared BEoL blank. The developed design allows the application of a tensile load to the BEoL structure by a lever mechanism. The lever was actuated by a microindenter whose indentation force is simultaneously quantified by a load cell. The applied force is subsequently used to parametrize an exhaustive FEM model. The intended cracking at a notch placed in the layered stack was verified by experimental testing. The outcome was validated by SEM imaging, confirming planar microcrack propagation from the notch through the silicon and its copper via structures.
Abstract
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